Ternary logic circuit

ABSTRACT

A ternary logic circuit, in which values of series-connected two controllable resistances to which plus potential and minus potential are respectively applied are controlled by a common input voltage. The output of the ternary logic circuit assuming one of three possible values in accordance with the value of the input voltage is obtained across a nonlinear load resistance connected across the ground and a junction between the two controllable resistances.

United States Patent Inventors Teruji Watanabe Kitudachi-gun; Hideo Yamamoto, Sagamihara-shl, both of, Japan Appl. No. 3,080 Filed Jan. 15, 1970 Patented Aug. 1'], i971 Assignee Koltusai Dendiln Denwa Kabushiki Keisha Tokyo-to,.lapnn Priority Jan. 20, 1969 Japan 44/3517 TERNARY LOGIC CIRCUIT 3 Claims, 5 Drawing Figs.

US. Cl. 307/206, 307/209, 307/255, 307/258 Int. Cl. H03": 19/ 10,

[50] Field ol'Searcll {56] References Cited UNITED STATES PATENTS A 3,027,464 3/1962 Kosonocky 307/209 3,492,496 1/1970 Callan 307/209 Primary Examiner-Donald D. Forrer Assistant Examiner-B. P. Davis Attorneys-Robert E. Burns and Emmanuel .l. Lobato ABSTRACT: A ternary logic circuit, in which values of seriesconnected two controllable resistances to which plus potential and minus potential are respectively applied are controlled by a common input voltage. The output of the ternary logic circuit assuming one of three possible values in accordance with the value of the input voltage is obtained across a nonlinear load resistance connected across the ground and a junction between the two controllable resistances.

PATENTEDAUBIYIQII SHEET 1 BF 2 3.600.603

IRESISMNCE CON RES.

1 RL J I E 7 a v neil 'fuc 1 7 Vi I2 o g CONE 1 {i V R58 -R2 -52 INPUT VOLTAGE (1/) Fig. I Fig. 2

.ICURRENT PATENTED ml 1 m SHEET 2 (IF 2 INPUT VOLTAGE TERNARY LOGIC CIRCUIT practice.

The principle, construction and operation of the ternary logic circuit of this invention will be better understood from the following detailed discussion in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram for describing the principle of this invention;

FIG. 2 shows characteristic curves explanatory of the characteristics of controllable resistances used in the circuit shown in FIG.1;

FIG. 3 shows a characteristic curve explanatory of the characteristic of a nonlinear load resistance used in the circuit shown in FIG. 1;

FIG. 4 shows input-output characteristics of the circuit shown in FIG. 1; and

FIG. 5 is a circuit diagram for illustrating an embodiment of this invention.

With reference to FIG. 1, a ternary logic circuit of this invention comprises a first controllable resistance R,, a second controllable resistance R, connected in series to the first controllable resistance R,, a DC source +E, applying a plus DC voltage to the first controllable resistance R,, a DC source -'E applying a minus DC voltage to the second controllable resistance R and a load resistance RL connected across the ground E and a junction J, between the first controllable resistance R, and the second controllable resistance R An input voltage V, supplied across terminals 1 and la is commonly applied to respective input terminals I, and I, of the first and second controllable resistances R, and R,. In this case, the value of one of the first and second controllable resistances R, and R increases continuously as the value of the input voltage V, increases as shown by a curve a in FIG. 2. On the other hand, the value of the other of the first and second controllable resistances R, and R, decreases continuously as shown by a curve b in FIG. 2. Moreover, the load resistance RL has a double N-shaped nonlinear voltage-current characteristic as shown in FIG. 3 in which the load resistance RI. has a N- shaped voltage-current characteristic in each of plus and minus current regions. In other words, the terminal voltage V, of the load resistance RL assumes a low value until the current I of the load resistance RL exceeds a plus threshold level 1,, or a minus threshold level I,,, after starting from zero and assumes one of two possible values when the current I of the load resistance means RL exceeds the plus and minus threshold levels I,,, and I The two possible values are substantially constant plus and minus values each higher than the low value. In this case, the plus constant value is obtained when the current I exceeds the plus threshold level I,,,, and the minus constant value is obtained when the current I exceeds the minus threshold level I,,,.

To obtained a preferred input-output characteristic described below, it is desirable that each of two peak voltages V,,, and V5, in a voltage-current curve 0 is small as far as possible. Moreover, it is desirable that the slope of the curve c is sharp as far as possible when the terminal voltage V, of the load resistance RL exceeds either a minimum voltage V or V,,,. In the following description, it is assumed that these conditions are satisfied for simple description.

In operation, the voltages of the DC sources +E, and -13, are so adjusted that the current I flowing through the load resistance RL is zero when the input voltage V, is zero. Accordingly, the potential of the junction J, is also zero in this case. In this condition, the input voltage V, of positive pulse is applied across terminals 1 and la as shown in FIG. 2. in accordance with this application of the input voltage V,, the value of the first controllable resistance R, increases along the curve a and reaches a value r, while the value of the second controllable resistance R decreases along the curve I) and reaches a value r Accordingly, since the potential of the junction .1, is shifted to a minus value from zero, the current I flows from the ground E to the junction J,. In this case, the output voltage V, generated across the load resistance RL is determined in accordance with the characteristic shown in FIG. 3. When the input voltage V, increases to the plus side from zero, the current I increases to the minus side. Since the operating point of the load resistance RL exists between points 0 and p, on the curve c until the current I exceeds a value I,,,, the output voltage V, increases gradually up to a value V,,,. However, the value of the output voltage V, is very low in this condition. When the current I exceeds the value I,,, in accordance with increase of the input voltage V,, the operating point of the load resistance means RL jumps over a negative resistance region (from the point P, to a point V,) to a point B along a load line m of the load resistance means RL. In this case, the slope of the load line m can be approximately deemed as the value of the load resistance RL. Accordingly, the value of the output voltage V, increases suddenly from the value V,,, to a value V,,. In a case where the input voltage V,

further increases to the minus side, since the curve 0 has a sharp slope at the outside of the point B, the output voltage V, is substantially constant while the increase of the output voltage V, is negligible.

The above-mentioned operation is a section O-M of an input-output characteristic shown in FIG. 4 in which the abscissa is the value of the input voltage V, and the ordinate is the value of the output voltage V,. In this case, a value V,, is the value of the input voltage V, when the current I is equal to the value I,,,. As understood from this characteristic, (1) the output voltage V, assumes a very low value substantially equal to zero if the input voltage V, falls in a first region from zero to the voltage V (2) the output voltage V, jumps to the value V,, at a condition where the input voltage V, is equal to the voltage V and (3) the output voltage V, is substantially zero while it increases by insensible transitions if the input voltage V, increases in a second region exceeding the voltage V On the other hand, if the input voltage V, decreases from the second region (Vi V to zero along the curve c, the jump over the negative resistance region is started at the point V, shown in FIG. 3. This jumping is started in FIG. 4 at a value slightly shifted to zero from the value V This hysteresis characteristic is substantially negligible in comparison with the value V if the resistances of the controllable resistances R, and R are small as far as possible under nonoscillation of this circuit. Accordingly, a curve d shown in FIG. 4 can be substantially deemed as a single curve.

The above operations relate to a case where the input voltage V, is plus. However, if references P,, V ,1, B and V,, etc. shown in FIG. 3 are respectively replaced by references P V,, In, A and V etc. in the same FIG. 3, a section ON of the inputoutput characteristic corresponding to a case where the input voltage V, has a minus polarity can be obtained as shown in FIG. 4. In this case, the value V is the value of the input voltage V, in a case where the current I is equal to the value I and a value V, shown in FIGS. 3 and 4 can be deemed as the value of the output voltage V, in a region where the input voltage V, exceeds the value V Accordingly, the value of the output voltage V, of the circuit assumes (l) substantially zero in a case where V,-, V, V (2) substantially the value V,, in a case where V, V and (3) substantially the value V, in a case V, V The values V V V,, and V characterizing the characteristic of this circuit shown in FIG. 1 are determined by the threshold currents I,,, and 1,, and the minimum voltages V,,, and V As described below, the nonlinear load resistance means RL can be realized by the use of a series-connection of Esakidiodes (tunnel diodes) so as to have the characteristic shown in FIG. 3. In this case, the values I and I,, can be determined as desired; and values V,,, and V can be varied by changing the material of the Esaki diodes or can be varied in a terraced manner by changing the number of series-connected Esaki diodes. As understood from above, the characteristic values V V V,, and V A can be varied in respective wide ranges. In this case, since the jumping speed at the values V and V are very high, the circuit of this invention performs a high speed ternary pulse-reshaping operation.

Moreover, ratios V /V and V,,/V,-, which are deemed as the amplification constant of this circuit are determined by the sensitivity of the controllable resistances R, and R (i.e.; the slope R/V of the curves a and b shown in FIG. 2). In other words, the amplification constant of this circuit becomes higher as the slope of the curves a and b becomes sharper. In an embodiment described below, transistors are used as the controllable resistances R, and R,. In this case, the amplification constant of this circuit becomes higher as the current amplification factor h becomes larger.

In the above description, it is assumed that the respective characteristics of the first controllable resistance R, and the second controllable resistance R, are shown respectively as the curves a and b in FIG. 2. However, the respective characteristics of the resistances R, and R may be respectively the curves b and a. In this case, the input-output characteristic of this circuit is shown as a dotted curve e shown in FIG. 4, in which the polarity of the output voltage V, is inversed against the curve d.

The circuit of this invention is a ternary pulse reshaping-amplifying circuit having the above mentioned function. Moreover, this circuit of this invention can be applied to perform ternary logical NOT f,,, ternary logical OR f ternary logical AND f,,,,,, ternary logical NOR f,,,,,- and ternary logical NAND f proposed by Post-Lukasiewicz. Conditions in this case will be described below.

Now, it is assumed that ternary digits are I," P" and and the relationship l I O is to be decided. In this case, if it is assumed that N logical variables each assuming one ofthree possible values 1," "D" and 0" are respectively designated by notations x,, x x,,, the above-mentioned ternary logical NOT f}, ternary logical OR fl ternary logical AND f,,,,,,, ternary logical NOR f,,,,, and ternary logical NAND f,,,,,,,, are defined respectively as follows:

In the circuit shown in FIG. I, the ternary logical digits l I and 0 correspond respectively to the values V 0, V,,. In this condition, the input voltage V, is one of the above mentioned logical variables x,, x,, x,,,.

In this case, if it is assumed that the value V is more than the value V and the value -V is less than the value V in the characteristic shown in FIG. 4, the ternary logical NOT f,, corresponds to the curve d. In the case of the curve e, the circuit of this invention can be used as a simple reshaping-amplifying circuit for a ternary pulse signal in accordance with an equivalent function.

If it is assumed that the sum of N different variables corresponds to the input voltage V,, the curve d corresponds to the ternary logical NOR fl and the curve e corresponds to the ternary logical OR f in a case where (l) the value V is more than a value (N-I) V,,, (2) a value (V,,(N1) V,,) is more than the value V and (3) the value V is less than a value (N1)V,, and more than a value NV,,. On the other hand, in a case where (I) the value V is more than a value (N-I) V (2) the value V is less than a value NV, and less than a value (Nl)V,,, and (3) the value V is less than a value ((N1)V,, V,,), the curves d and e correspond respectively to the ternary logical NANDf and the ternary logical AND f With reference to FIG. 5, an embodiment of this invention comprises a PNP transistor TR, used as the first controllable resistance, a NPN transistor TR, used as the second controllable resistance, and a series-connection of two sets of Esaki diodes ED, and ED, which are oppositely series-conected to each other and used as the load resistance RL. In this case, each of the sets of Esaki diodes ED, and ED, comprises a plurality of Esaki diodes which are series-connected to one another in the same direction. The respective emitter-collector paths of the transistors TR, and TR, are series-connected to each other. The series-connection of the two sets of Esaki diodes ED, and ED, is connected across the ground E and a junction J between collectors of the transistors TR, and TR,. A DC source +E, applies a plus voltage to the emitter of the transistor TR,, and a DC source -E, applies a minus voltage to the emitter of the transistor TR An input voltage V, is applied through respective resistors R and R to bases of the transistors TR, and TR, respectively. The output voltage V is obtained across the series-connection of Esaki diodes ED, and ED In this embodiment, the respective resistances of the emitter-collector paths of the transistors TR, and TR, are controlled by the input voltage V, and varied as shown by the curves a and b in FIG. 2. The voltage-current characteristic of the load resistance comprising the seriesconnection of the two sets of Esaki diodes ED, and ED, varies along the curve 0 shown in FIG. 3. In this case, a right half of the curve c divided by the ordinate corresponds to the forward characteristic of the set of Esaki diodes ED,, and a left half of the curve 0 corresponds to the forward characteristic of the set of Esaki diodes ED,. Accordingly, all operations described with reference to FIGS. 1, 2 and 3 can be applied without modification to this embodiment shown in FIG. 5, and the input-output characteristic of this embodiment can be designated similarly by the curve d shown in FIG. 4. As previously described, values V V-,-,, -V,, and V can be varied in respective wide ranges in this embodiment. Moreover, since jumping operation caused at each of the values V and V of the input-output characteristic is very high due to the negative resistance of the Esaki diode, high frequency response can be obtained in this embodiment.

The embodiment shown in FIG. 5 is suitable to realize a failsafe logical circuit. If a resistance equal to the resistance of the transistor TR, or TR, in a case of no input signal is inserted in series at the collector of the transistor TR, and TR,, the output voltage V, is always zero in a case of short or open of the emitter-collector path of each of the transistors TR, and TR, In another main fault where the sets of Esaki diodes ED, and ED are short-circuited, the output voltage V becomes zero. To make the output voltage V, zero at the open-circuit of the Esaki diodes ED, and ED,, two ternary logic circuits of this invention having a pair of common output terminals J, and E may be used.

In the above description, it is assumed that the nonlinear characteristic of the load resistance is a double N-shaped voltage-current characteristic. However, the ternary logic circuit of this invention can be also constructed by the use of a load resistance having a double S-shaped voltage-current characteristic.

What we claim is:

l. A ternary logic circuit comprising:

a first controllable resistance whose resistance increases as the value of the input voltage thereof increases;

a second controllable resistance connected in series to the first controllable resistance, the resistance of the second controllable resistance decreasing as the value of the input voltage thereof increases;

a DC source operatively connected to the series-connection of the first and second controllable resistances to apply a plus voltage to one of the first and second controllable resistances and to apply a minus voltage to the other of the first and second controllable resistances;

means for applying a common input voltage to the first and second controllable resistances; and a load resistance connected across the ground and a junction between the first controllable resistance and the second controllable resistance, the load resistance having a nonlinear current-voltage characteristic in which the terminal voltage of the load resistance assumes a low value until the current of the load resistance exceeds a plus or minus threshold level after starting from zero and assumes one of plus and minus substantially constant possible values each higher than the low value when the current of the load resistance exceeds the plus and minus threshold levels respectively; whereby an output voltage developed across the load resistance is so controlled in accordance with the input voltage that the output voltage assumes substantially zero when the input voltage assumes a value included in a first voltage-range between a predetermined plus voltage and a predetermined minus voltage, that the output voltage assumes a substantially constant plus voltage when the input voltage assumes a value included in one of a second voltage range and a third voltage range excluded from the first voltage-range to plus side and minus side respectively, and that the output voltage assumes a substantially constant minus voltage when the input voltage assumes a value included in the other of said second voltage-range and said third voltage-range.

2. A ternary logic circuit according to claim I, in which the first controllable resistance and the second controllable resistance are respectively a PNP transistor and a NPN transistor, respective emitter-collector paths of the transistors being connected in series, the input voltage being applied to both bases of the transistors.

3. A ternary logic circuit according to claim 2, in which the load resistance comprises two sets of Esaki diodes connected in series to each other in opposite directions, each of the sets of Esaki diodes comprising a plurality of Esaki diodes connected in series to one another in the same direction. 

1. A ternary logic circuit comprising: a first controllable resistance whose resistance increases as the value of the input voltage thereof increases; a second controllable resistance connected in series to the first controllable resistance, the resistance of the second controllable resistance decreasing as the value of the input voltage thereof increases; a DC source operatively connected to the series-connection of the first and second controllable resistances to apply a plus voltage to one of the first and second controllable resistances and to apply a minus voltage to the other of the first and second controllable resistances; means for applying a common input voltage to the first and second controllable resistances; and a load resistance connected across the ground and a junction between the first controllable resistance and the second controllable resistance, the load resistance having a nonlinear current-voltage characteristic in which the terminal voltage of the load resistance assumes a low value until the current of the load resistance exceeds a plus or minus threshold level after starting from zero and assumes one of plus and minus substantially constant possible values each higher than the low value when the current of the load resistance exceeds the plus and minus threshold levels respectively; whereby an output voltage developed across the load resistance is so controlled in accordance with the input voltage that the output voltage assumes substantially zero when the input voltage assumes a value included in a first voltage-range between a predetermined plus voltage and a predetermined minus voltage, that the output voltage assumes a substantially constant plus voltage when the input voltage assumes a value included in one of a second voltage range and a third voltage range excluded from the first voltage-range to plus side and minus side respectively, and that the output voltage assumes a substantially constant minus voltage when the input voltage assumes a value included in the other of said second voltagerange and said third voltage-range.
 2. A ternary logic circuit according to claim 1, in which the first controllable resistance and the second controllable resistance are respectively a PNP transistor and a NPN transistor, respective emitter-collector paths of the transistors being connected in series, the input voltage being applied to both bases of the transistors.
 3. A ternary logic circuit according to claim 2, in which the load resistance comprises two sets of Esaki diodes connected in series to each other in opposite directions, each of the sets of Esaki diodes comprising a plurality of Esaki diodes connected in series to one another in the same direction. 